1. Technical Field
Various embodiments of the present disclosure relate to a Look Up Table (LUT) including a nonvolatile memory element, and more particular to an LUT that is used by a plurality of applications, a Field Programmable Gate Array (FPGA) including the LUT, and a method for designing the FPGA.
2. Related Art
A Field Programmable Gate Array (FPGA) is a type of Programmable Logic Device (PLD) that is widely used to design digital circuits that perform specific operations through the programming of the PLD.
An FPGA includes configurable logic blocks (CLBs), input/output blocks (IOBs), and configurable connection circuits that connect the CLBs and the IOBs. The FPGA may further include delay locked loops (DLLs), random access memories (RAMs), and the like.
A CLB includes at least two sub-circuits, one of which is a register circuit such as a flip-flop, the other of which is a function generator circuit that can be implemented with an LUT.
FIG. 1 shows a conventional LUT.
The conventional LUT includes a Static Random Access Memory (SRAM) array 10 and a switch array 20. The SRAM array 10 includes a plurality of SRAMs.
The switch array 20 sets a path so that data stored in any one of the plurality of SRAMs is output as an output signal OUT in accordance with decoding signals A, B, and C.
Such a conventional LUT is easy to implement a combinational logic circuit or a sequential logic circuit, but when the power is interrupted, data stored in the SRAMs are lost and thus the SRAMs must be newly programmed.
Also, when a plurality of applications share one LUT, SRAMs in the LUT must be reprogrammed whenever an application using the LUT is changed.
Since the conventional LUT and an FPGA including the LUT cannot be programmed for a plurality of applications in advance, they must be reprogrammed when an application using the LUT is changed.
To avoid reprogramming an LUT in the conventional FPGA, the FPGA must include as many LUTs as applications programmed on the FPGA, and the FPGA must use the LUTs in parallel. In this case, the size of the FPGA depends on the number of applications. When the FPGA must accommodate a large number of applications, the size of the FPGA can be excessive.